tiling
4 stories filed under tiling on Beyond Market Intelligence. The newest of them: “From naive GEMM to FlashAttention: a free code-first GPU kernel series”, “Explore how Triton simplifies custom GPU kernels for faster ML workflows.”, and “Gradient accumulation speed varies more than expected across GPU setups”. Most GPU kernel tutorials treat optimization as a black art. Triton shines when the bottleneck is memory-bound rather than compute-bound. Acme AI is the next-generation, AI-powered spreadsheet platform built to replace Excel and redefine how analysts, data scientists, and enterprise teams work… The list below is every tiling story on Beyond Market Intelligence, newest first.
From naive GEMM to FlashAttention: a free code-first GPU kernel series
Most GPU kernel tutorials treat optimization as a black art. This series opens it up. The insight that performance is a data-movement problem first, compute second, reframes everything. Building FlashAttention from scratch, where tiling avoids writing the full attention matrix to memory, is a perfect worked example. The 44-session roadmap covers GEMM through Hopper architecture, with live profiling at every step. If you write production kernels, this is the kind of resource worth contributing feedback to.
Explore how Triton simplifies custom GPU kernels for faster ML workflows.
Triton shines when the bottleneck is memory-bound rather than compute-bound. Operations like element-wise fusions, reductions, or attention that stall on data movement are prime candidates for custom kernels. Harshwardhan Fartale's early-access book gets this right: it focuses on practical acceleration, not theory. If you're stuck waiting on a stubborn layer, that's the signal to explore. For those new to kernel work, pairing this with broader distributed training context, like the guide on LLM training algorithms, helps frame when optimization matters most.
Gradient accumulation speed varies more than expected across GPU setups
Conventional wisdom says a batch of four is a batch of four, but this test on LoRA with Qwen3-1.7B shows otherwise. The user found that on a T4, running four micro-batches before one optimizer step was 17% slower than a single physical batch of four. On an L4, that gap stretched to 41%. The difference is execution shape, not just optimization math. Treating effective batch and physical batch as the same knob is a mistake.
From silicon to inference: building YOLO26n from scratch on a Raspberry Pi
Forget high-level frameworks for a moment. This is the real deal: YOLO26n inference built from scratch in ARM64 Assembly and C, running on a Raspberry Pi 4. The author didn't just call a library; they rewrote the engine, diving into NEON SIMD, Winograd convolutions, and custom micro-kernels to squeeze every cycle out of the hardware. It's a bold move that shows genuine grit.